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Forum Post: Not getting S124 to Subosc-Speed mode

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I'm running on the DK-S124 board with my milliammeter on J3.  The current only goes down to 700 uA when I run the following function with an argument of 10000 in an infinite for loop: #define WUPEN_AGT1_UNDERFLOW_MASK (1 28) // Wake the processor up on AGT 1 underflow only. void sleepProcessorMs ( uint32_t ms) { static const cgc_system_clock_cfg_t normalClockConfig = { .iclk_div = BSP_CFG_ICK_DIV, .pclkb_div = BSP_CFG_PCKB_DIV, .pclkd_div = BSP_CFG_PCKD_DIV }; static const cgc_system_clock_cfg_t slowClockConfig = { .iclk_div = CGC_SYS_CLOCK_DIV_1 , .pclkb_div = CGC_SYS_CLOCK_DIV_1 , .pclkd_div = CGC_SYS_CLOCK_DIV_1 }; static bool state = false; /* Stop the watch crystal clock. */ g_cgc. p_api - clockStop ( CGC_CLOCK_SUBCLOCK ); /* Wind up our timer. */ g_timer0. p_api - periodSet (g_timer0. p_ctrl ,ms, TIMER_UNIT_PERIOD_MSEC ); /* * Do the rest of this with the interrupts disabled so that we don't get * stuck in software standby mode if this code is breakpointed and so that * we don't service any complicated interrupts with the clock running slow. */ __disable_irq(); /* Start our timer. */ g_timer0. p_api - start (g_timer0. p_ctrl ); /* Switch the clock to the LOCO then drop the processor to low speed mode. */ g_cgc. p_api - systemClockSet ( CGC_CLOCK_LOCO ,( cgc_system_clock_cfg_t *)&slowClockConfig); g_lpm0. p_api - operatingPowerModeSet ( LPM_OPERATING_POWER_LOW_SPEED_MODE , LPM_SUBOSC_SELECT ); /* Configure the processor to exit low-power mode on AGT 1 underflow. */ g_lpm0. p_api - wupenSet (WUPEN_AGT1_UNDERFLOW_MASK); /* Put the processor into software standby mode. */ g_lpm0. p_api - lowPowerCfg ( LPM_LOW_POWER_MODE_STANDBY , LPM_OUTPUT_PORT_ENABLE_RETAIN , LPM_POWER_SUPPLY_DEEPCUT0 , LPM_IO_PORT_NO_CHANGE ); g_lpm0. p_api - lowPowerModeEnter (); /* Raise the processor to high-speed mode then switch the clock back to the HOCO. */ g_lpm0. p_api - operatingPowerModeSet ( LPM_OPERATING_POWER_HIGH_SPEED_MODE , LPM_SUBOSC_OTHER ); g_cgc. p_api - systemClockSet ( CGC_CLOCK_HOCO ,( cgc_system_clock_cfg_t *)&normalClockConfig); /* And we're out of the touchy bits. */ __enable_irq(); /* Use 'scope on P1_6 to see how often this exits. */ state = !state; g_ioport. p_api - pinWrite ( IOPORT_PORT_01_PIN_06 ,state); } Aside from what you see here, the only other peripherals that are ever opened are SCI 0 (in clock-synchronous SPI mode with the DTC drivers), GPT channels 1 and 2, and DAC channel 0.  The DAC is currently closed.  GPT channel 2 is stopped.  No transfers are in progress on SCI 0. My oscilloscope tells me that both crystal oscillators are stopped.  P1-6 toggles every 10 seconds as expected. What is keeping me from getting the power down to the 10 uA level as the datasheet suggests is possible (see the last line in the table in section 2.2.9)? Thanks!

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