well now, I've been tracking this length problem and things are making zero sense at this point. Need another set of eyeballs. Ive got the I2S line set up as 8 bit data with 16 bit words. What I'm seeing appears to be that way with left justified 8 bit data in 16 bits per channel. My buffers are set up as: Sample_t Samples[MAX_DAC_SAMPLES][2]; so the [2] of that is channel. these are 512 samples here so MAX_DAC_SAMPLES == 512 I want to see what I'm getting on the I2S bus and when so I fill that buffer in a for loop Samples[i][0] = (Sample_t)(i>>8); Samples[i][1] = (Sample_t)i; then I write that to the I2S with: BytesToWrite = (UINT)nSamples*2*sizeof(Sample_t); // we have 2 channels of nSamples at Sample_t size (1 or 2 bytes). g_i2s0.p_api->write(g_i2s0.p_ctrl, (uint8_t *)Samples, (uint16) BytesToWrite); nSamples is 512 here * If Sample_t is int8 sized (BytesToWrite=1024), what I see on the bus is chan1 (WSL low)=0, chan2 (WSL high)=1, chan1=2,chan2=3 and so on, i.e. this is picking this buffer every other byte but only writing 256 samples (both chan 1 and 2). * if Sample_t is int16 sized (BytesToWrite=2048), what I see on the bus is chan1=chan2=0 for the first 256 samples are zero and chan1=0,chan2=1 for the next 256 samples. This writes the correct number of samples out there * If I write these in: Samples[i][0] = Samples[i][1] = (Sample_t)i; // i.e. both channels the same with Sample_t as int8 (BytesToWrite=1024), what I see on the bus is chan1=0, chan2=0, chan1=1,chan2=1, chan1=2,chan2=2 and so on, i.e. this is picking this buffer every byte but only writing 256 samples. Byte order of the 16 bit version: Byte order of the 8 bit version: so the questions: 1) what byte order is this thing picking in really? 2) It might be that it wants 16 bit words even if it's only using 8? 3) Exactly when does the ISR callback get fired in relation to the output? When that comes back, does that mean the buffer that I wrote can now be rewritten with something else without it messing up the last of the transfer (i.e. what's the hardware FIFO size here)? If I now do another write to the I2S, does that hang until the thing is done with the prior one?
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