Hi rjl, The hardware manual for SSI says that FIFO register should be accessed in 64-bit units regardless of the data word length, however the driver should automatically adjust the size. The ISR callback gets fired when the FIFO queue is 'almost' empty. It has 8 stages in S7G2 and S3A7. 'Almost' means that the ISR callback gets fired when at least N stages are empty (by default when 2 stages). You can supply new data in this callback without worry that previous transfer won't be finished. Regards, adboc
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