Forum Post: RE: http server compile error: 'g_fx_media0' undeclared (first...
Hello Rocco, Did you re-generate the project content after swapping out the .xml file? Regards
View ArticleForum Post: RE: http server compile error: 'g_fx_media0' undeclared (first...
Just to be sure I regenerated and am still having the same issue.
View ArticleForum Post: RE: Can't get TCP socket to connect on S7G2
Thank you for all your help. I used the examples from your post and I have it working now.
View ArticleForum Post: RE: http server compile error: 'g_fx_media0' undeclared (first...
Hello Rocco, Please delete synergy_gen folder inside src directory and re-build your project. Alternatively, you can investigate the following example project I've put together (remember to replace the...
View ArticleForum Post: SSI (I2S) output format. What is it and how do you influence it?
Using SSP 1.2, I don't see a way to influence what format is being put out on I2S (SSI) other than word length and size. does it do MSB or LSB? Nothing in any SSP documentation that tells what the...
View ArticleForum Post: HAL layers for SSI and buffers
The SSP documentation makes an oblique reference to internal buffers and FIFOs for R_SSI_Write() saying: "This function resets the transfer if the transfer interface is used, or writes the length of...
View ArticleForum Post: RE: ETH_IRQ14 Pin of PhyEthernet Controller
Don't know how the LED is controlled and if it indicates that the interface is 100% ok, but: Have you tried different drive strengths on the RMII outputs?
View ArticleForum Post: RE: http server compile error: 'g_fx_media0' undeclared (first...
Karol, Deleting the synergy_gen folder didn't help. If I double click or try to save as on the link in your reply, nothing seems to happen. Thanks
View ArticleForum Post: RE: http server compile error: 'g_fx_media0' undeclared (first...
Karol, Downloading the zip file must be a problem with Chrome. I was able to download it using a different browser. Thanks.
View ArticleForum Post: RE: When will the S5 series be available?
Also is there an estimate on when a S5 dev kit will be released ?
View ArticleForum Post: RE: ETH_IRQ14 Pin of PhyEthernet Controller
Hello Karol, hello josh22, thank you for your replies! Now I did both: adding BSP_BOARD_S7G2_SK and setting RMII pins to high strength (like it is in the SK example) and now LAN works fine :-) Thanky...
View ArticleForum Post: RE: Supporting a new touch controller chip
Hello, I found out that my touch panel uses FT5406 driver. The problem was that WAKE signal (not included in the framework) has to be driven to high level. However I had to swap the horizontal and...
View ArticleForum Post: RE: http server compile error: 'g_fx_media0' undeclared (first...
Hello Rocco, Did you manage to build the example I've sent? Regards
View ArticleForum Post: RE: SSI (I2S) output format. What is it and how do you influence it?
Hello, These answers are found in the device manual for a specific device (i.e. S7G2 User's Manual), rather than the SSP. SSP User's manual only documents what's accessible through the driver. From...
View ArticleForum Post: RE: HAL layers for SSI and buffers
Hello, The FIFO is 8-stage for both, transmitter and receiver. It may not be clear from the sentence you quoted, by the driver stores the pointer to the current buffer in the control structure - no SSP...
View ArticleForum Post: RE: When will the S5 series be available?
Hello, Distribution channels should have access to first S5 kits in March. Individual availability depends on the distributor. Regards
View ArticleForum Post: RE: USB Host - Problems with host class instance SSP1.1.3
Our problem was solved removing every tx_thread_relinquish() call there was (and replacing it with a sleep just in case). Did you check that every call to this function is removed? I think I recall...
View ArticleForum Post: RE: Supporting a new touch controller chip
Hello, Supplied driver should be compatible with all devices from FT5x06 family. I reckon that either state of "wake" function upon boot is determined by the firmware version on your Focaltech device...
View ArticleForum Post: RE: HAL layers for SSI and buffers
FIFO: I've got 8 bit mono PCM data coming in. I want to set up for 16 bit per channel going out. Do writes then point to the 8bit (stereoized) PCM or do I need to expand that to 32 bit stereo buffers...
View ArticleForum Post: RE: HAL layers for SSI and buffers
Hello, Your solution looks very similar to what Audio Playback Framework is doing already. Detailed User Guide for this framework can be found in SSP User's Manual (v0.96), section 4.2.2. I'm also...
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