Hi adboc How the USB bootloader will jump from bootloader to this image app ?
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Forum Post: RE: Questions about the Synergy Flash Loader Add-on
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Forum Post: S5D9 running code from SDRAM / Flash
Our SW people would like to have a larger-than-2MB program code for our application. From what I gather, using external flash for running code is pretty slow. QSPI max clock is 60MHz and it takes 8 cycles to load an 32bit instruction in. To add insult to injury, flash cache doesn't seem to cover QSPI flash. Ouch. A better solution then would likely to be to use a SDRAM or a parallel flash. This would bump maximum effective speed from 7.5MHz max on QSPI to 60MHz on 16-bit SDRAM/Flash, presuming you could find a fast enough chip. Does the S5 cache instructions from the SDRAM or External CS memory?
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Forum Post: RE: S5D9 running code from SDRAM / Flash
Olli, The S5 does not cache instructions from the external address spaces. The cache is a 'FLASH CACHE' and only is effective for the on-chip flash address space. -Gary
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Forum Post: RE: Secondary network interface does not come up if primary (Ethernet) not connected
Hi Jeremy, Thanks for the info. I pulled down the new pack and will take a look at installing it this afternoon. It must have been posted recently since I did check before I updated to the latest SSP in our project. I have a theory about why the DHCP Server responses aren’t being transmitted and want to look at that first. We have some Python scripts that modify framework code in synergy directory tree prior to the build to add the Redpine enhancements and I will probably need to fix those if any of the Redpine files in the new pack that we modify with the scripts are different. thanks, pete
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Forum Post: RE: Keyboard on the Screen of an S5
Hello Maria, this can be done by using the modal dialog execution. Please refer to the: X-Ware™ Component Documents for Renesas Synergy™ > > GUIX User Manual > Chapter 3: Functional Overview of GUIX > Modal Dialog Execution p.18 Best regards, anper
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Forum Post: RE: S5D9 running code from SDRAM / Flash
Ok, I see. The flash cache is pretty limited too, 256 bytes does not go very far with regards to reducing random accesses. I think our SW team has to either a) figure out how to make the code run from the internal 1MB/2MB flash or b) we need to look at a microprocessor which is actually designed to run code from an external memory.
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Forum Post: RE: S5D9 running code from SDRAM / Flash
Hi Olli, You can go up to S7G2 device for 3 and 4MB of flash. Regards
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Forum Post: RE: S5D9 running code from SDRAM / Flash
The bean counter in me disapproves. Could you please confirm to me how running code from external memory works? In worst case each word is fetched completely independently with precharge and activate in between. As an example, Alliance AS4C4M16SA 166MHz part would work out to tRCD = 3 clk, tCL = 3clk, tRAS = 5clk, tRP=3clk So if we do this in the most un-optimal way possible, it'd be tRAS + tRP 5+3 = 8 cycles for each word.. Hardly optimal at 66.7ns / pop. To make things even worse, you need two words so it'd be 16 clocks or 133.3ns for two accesses or 7.5MHz instruction clock! Figure 15.58 of the S5D9 handbook implies this is the case. It's possible to do multiple reads at one time so grabbing two words for one instruction back to back, it'd be slightly less painful at 9 clocks or 13.3MHz instruction clock. Figure 15.64 implies "PRA+ACT" is always done for multiple reads. Ideally the SDRAM controller "knows" about rows and doesn't deselect the device in-between accesses, you'd be looking at 4 clocks per long or 30MHz instruction clock. For comparison the internal flash can do 3 cycles @ 120MHz clock so 40MHz instruction clock cycle worst case. Obviously the flash cache does prefetching and some general caching so the average instruction rate would be a fair bit better than that.
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Forum Post: FTP Server on PK board wont accept new files
If I "put" a file from Windows to the board, the response is "open failed". If the file already exists on the PK board, them the "put" will transfer the file. Note that in FX_FILE_OPEN you cannot open a file for write if it doesn't exists - you have to FX_FILE_CREATE it first. Can that be fixed? Note- Windows FTP does not support PASV mode so that can be it. Thanks Larry
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Forum Post: R_DAC fails to build on S1JA in SSP 1.5.0-rc.1
The R_DAC module will fail to build on the S1JA in SSP 1.5.0-rc.1 Issue: The R_ADC configuration property "Output Amplifier" is incorrectly populated by the configurator for the S1JA in SSP 1.5.0-rc.1. This creates a build error since the incorrectly populated value fails to compile. Workaround: None available. Suggestion is to use the DAC8 as an alternative, if possible. ID # 12903
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Forum Post: SDRAM initialization on S5DP
We have a application that needs a lot of dynamic memory. We're developing on a PK-S5D9 board so we want to it using the 32MB SDRAM on the board and move the heap to SDRAM. A while ago, a comment was written by Gary J.. "No, that's not all - please not that the SDRAM initialization occurs AFTER the c startup. This won't work. You need to initialize the SDRAM after the I/O and Clock tree is initialized and before the c startup stuff. -Gary" Why is it necessary to init the SDRAM that early. If I only want to put the heap there, does it still have to occur prior to the first dynamic allocation (ie "alloc" or "new"). The stack will stay allocated in the S5's sram. Thanks Larry
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Forum Post: RE: HAL CRC driver fails with SSP_ERR_ASSERTION when starting address is 0
Thank you!
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Forum Post: RE: SDRAM initialization on S5DP
Hi Larry, If you are using C++ any static constructors will be called before main() executes and if any of these constructors use heap the allocation will fail. Again, I don NOT recommend using the heap from the standard run-time library, it is not thread safe or deterministic. I recommend writing wrapper functions for malloc, calloc and free that use the byte pool APIs as these are designed for real time systems and are thread safe and deterministic. -Gary
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Forum Post: RE: SDRAM initialization on S5DP
Well, I was trying to set up the System Bus pins on the PK board and had to look at the schematic. I don't think there is any SDRAM. I guess I was thinking of a DK board I use to use. Does that sound right. But it the bsp_init code that calls bsp_sdram.c init is called way before anything in user code is called, isn't it? They've protected the malloc calls for now - it's a port of some open source that they don't want to/can't easily rewrite. Thanks again Larry
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Forum Post: SSP_INVALID_ARGUMENT failure from flash erase() API on s3a3
I've been using the same flash algorithm for the S3A7, S3A1, and S5D9 for about a year now. We just started using the S3A3; and the following piece of code is failing with SSP_ERR_INVALID_ARGUMENT. This same piece of code runs without a hitch in the other MCUs. I'm running this on the TB-S3A3 board, R7FS3A37A3A01CFB, with SSP 1.4 and e2 Studio Version: 6.2.0 Build Id: R20180102-1636 with IAR toolchain 8.x. __disable_irq(); ssp_err = g_flash0.p_api->erase(g_flash0.p_ctrl,fcb->currentEraseBlockAddress, ERASE_ONE_BLOCK); __enable_irq(); I've run this in the debugger and verified the erase block address value and the number of blocks at the time of the erase() call. The erase block value is 0x48000 and the number of blocks is 1. 0x48000 is a multiple of 2KB, which is the erase granularity. Before the erase() call I make sure the access window is cleared. Is there something different about the S3A3's flash update procedure that I haven't taken into account? g_flash0 appears valid also, at least I don't see anything obviously wrong. g_flash0 const flash_instance_t {...} (Hex) 0xde5c p_ctrl flash_ctrl_t * 0x200088d8 (Hex) 0xde5c *p_ctrl flash_ctrl_t 0x0 (Hex) 0x200088d8 p_cfg const flash_cfg_t * 0xdda0 (Hex) 0xde60 data_flash_bgo bool 0x1 (Hex) 0xdda0 p_callback void (*)(flash_callback_args_t *)0x9081 (Hex) 0xdda4 p_extend const void * 0x0 (Hex) 0xdda8 *p_extend const void 0x0 (Hex) 0x0 p_context const void * 0xde5c (Hex) 0xddac *p_context const void 0x0 (Hex) 0xde5c irq_ipl uint8_t 0x2 (Hex) 0xddb0 err_irq_ipl uint8_t 0x0 (Hex) 0xddb1 p_api const flash_api_t * 0xdb18 (Hex) 0xde64 open ssp_err_t (*)(flash_ctrl_t * const, const flash_cfg_t * const) 0x757f (Hex) 0xdb18 write ssp_err_t (*)(flash_ctrl_t * const, const uint32_t, const uint32_t, const uint32_t) 0x7647 (Hex) 0xdb1c read ssp_err_t (*)(flash_ctrl_t * const, uint8_t * const, const uint32_t, const uint32_t) 0x76af (Hex) 0xdb20 erase ssp_err_t (*)(flash_ctrl_t * const, const uint32_t, const uint32_t) 0x7731 (Hex) 0xdb24 blankCheck ssp_err_t (*)(flash_ctrl_t * const, const uint32_t, const uint32_t, flash_result_t * const) 0x7801 (Hex) 0xdb28 infoGet ssp_err_t (*)(flash_ctrl_t * const, flash_info_t * const) 0x79c9 (Hex) 0xdb2c close ssp_err_t (*)(flash_ctrl_t * const) 0x79fd (Hex) 0xdb30 statusGet ssp_err_t (*)(flash_ctrl_t * const) 0x7881 (Hex) 0xdb34 accessWindowSet ssp_err_t (*)(flash_ctrl_t * const, const uint32_t, const uint32_t) 0x78b1 (Hex) 0xdb38 accessWindowClear ssp_err_t (*)(flash_ctrl_t * const) 0x78bd (Hex) 0xdb3c reset ssp_err_t (*)(flash_ctrl_t * const) 0x78c5 (Hex) 0xdb40 updateFlashClockFreq ssp_err_t (*)(flash_ctrl_t * const) 0x7981 (Hex) 0xdb44 startupAreaSelect ssp_err_t (*)(flash_ctrl_t * const, flash_startup_area_swap_t, bool) 0x78f3 (Hex) 0xdb48 versionGet ssp_err_t (*)(ssp_version_t *) 0x7a4d (Hex) 0xdb4c Thanks for any assistance. tom
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Forum Post: RE: SSP_INVALID_ARGUMENT failure from flash erase() API on s3a3
It appears the erase() call is failing here. It looks like the only place the INVALID_ARGUMENT code is returned. #if (FLASH_CFG_PARAM_CODE_FLASH_PROGRAMMING_ENABLE == 0) FLASH_ERROR_RETURN((g_block_info.is_code_flash_addr == false), SSP_ERR_INVALID_ARGUMENT); #endif But the is_code_flash_addr value at this point is 'true'.
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Forum Post: RE: SDRAM initialization on S5DP
Larry, The PK board does not have any SDRAM - the boards that support SDRAM are the DK-S7G2 and the PE-HMI. If you look in the file system_S5D9.c you will see where the bsp_init() function is called. This is after the section copies are done. The SDRAM is initialized in the bsp-init() call so you can't use SDRAM for initialized variables unless use the R_BSP_WarmStart() function to initialize the SDRAM. This gets called before the section copy. -Gary
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Forum Post: Patch for bug fix in IAR Embedded Workbench v8.23.1
Notice: The IAR EW for Synergy, v8.23.1 release, has an accompanying file titled, "Patch for bug fix in IAR Embedded Workbench v8.23.1". The description of the patch and the related issue can be found in the Release Note on the same web page: https://synergygallery.renesas.com/media/products/25/306/en-US/r20ut4362eu0101-synergy-iar-wb-v8231-rel-note.pdf Section 7.4 of the Release Note describes the issue and fix (shown below). 7.4 Popup messages show up when downloading project to S3A7 During download, a project using flash loader in EWSYN may result in J-Link Driver popup messages offering the user option to Abort Debug Session. In such a scenario, download the CFlashMF3.mac file from Solutions Gallery and replace the file on your computer located at /arm/config/flashloader/Renesas and restart EWSYN to address the issue.
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Forum Post: RE: SSP_INVALID_ARGUMENT failure from flash erase() API on s3a3
Hi Tom, Did you open the flash_lp driver before attempting to erase the block? Did you enable the code flash programming in the properties tab? The following code works on the TB S3A3 with no issues: void hal_entry(void) { ssp_err_t ssp_err; g_flash0.p_api->open(g_flash0.p_ctrl, g_flash0.p_cfg); __disable_irq(); ssp_err = g_flash0.p_api->erase(g_flash0.p_ctrl,0x48000, 1); if (ssp_err != SSP_SUCCESS) __BKPT(); __enable_irq(); for(;;); } -Gary
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Forum Post: RE: SSP_INVALID_ARGUMENT failure from flash erase() API on s3a3
Gary, Yes, and (embarrassed) No. I did not enable codeflash programming. We use an S3A3 template project to derive all our other S3A3 projects from, and the template didn't have it enabled for some reason. All our other MCU template projects enabled it (I just checked). Thanks. tom
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